Automated CPU Design by Learning from Input-Output Examples
Authors: Shuyao Cheng, Pengwei Jin, Qi Guo, Zidong Du, Rui Zhang, Xing Hu, Yongwei Zhao, Yifan Hao, Xiangtao Guan, Husheng Han, Zhengyue Zhao, Ximing Liu, Xishan Zhang, Yuejie Chu, Weilong Mao, Tianshi Chen, Yunji Chen
IJCAI 2024 | Conference PDF | Archive PDF | Plain Text | LLM Run Details
| Reproducibility Variable | Result | LLM Response |
|---|---|---|
| Research Type | Experimental | We propose a new AI approach to generate the CPU design in the form of a large-scale Boolean function, from only external IO examples instead of formal program code. This approach employs a novel graph structure called Binary Speculative Diagram (BSD) to approximate the CPU-scale Boolean function accurately. Our approach generates an industrial-scale RISC-V CPU design within 5 hours, reducing the design cycle by about 1000 without human involvement. The taped-out chip, Enlightenment-1, the world s first CPU designed by AI, successfully runs the Linux operating system and performs comparably against the human-design Intel 80486SX CPU. Our approach even autonomously discovers human knowledge of the von Neumann architecture. We apply the proposed method to automatically design a 32-bit RISC-V CPU within 5 hours. The taped-out CPU successfully runs the Linux OS and performs comparably against the human-designed Intel 80486SX CPU. |
| Researcher Affiliation | Collaboration | Shuyao Cheng1,2,3 , Pengwei Jin1,2,3 , Qi Guo1 , Zidong Du1,4 , Rui Zhang1 , Xing Hu1,4 , Yongwei Zhao1 , Yifan Hao1 , Xiangtao Guan5 , Husheng Han1,2 , Zhengyue Zhao1,2 , Ximing Liu1,2 , Xishan Zhang1,3 , Yuejie Chu1 , Weilong Mao1 , Tianshi Chen3 , Yunji Chen1,2 1State Key Lab of Processors, Institute of Computing Technology, Chinese Academy of Sciences 2University of Chinese Academy of Sciences 3Cambricon Technologies 4Shanghai Innovation Center for Processor Technologies 5University of Science and Technology of China |
| Pseudocode | Yes | Algorithm 1 Learn the circuit logic with BSD Expansion |
| Open Source Code | No | The paper does not provide any concrete access information (e.g., repository link, explicit statement of release) for the source code of the methodology described. |
| Open Datasets | No | The paper mentions the source of IO examples: |
| Dataset Splits | No | The paper states that |
| Hardware Specification | Yes | The implemented program is executed on a Linux cluster including 68 servers, each of which is equipped with 2 Intel Xeon Gold 6230 CPUs. |
| Software Dependencies | No | The paper mentions using |
| Experiment Setup | Yes | For the partition stage, the maximal number of clusters for each output bit is set as 10 to control the scale of the generated BSD. For the expansion stage, the maximal width of BSD is set as 10, 000 to balance the BSD accuracy and expansion efficiency. For the merging stage, to determine the similarity between different nodes, the maximal sampling number per node is set as 1, 000, 000 to balance the reduction accuracy and sampling efficiency. |