Learning Semantic Representations to Verify Hardware Designs
Authors: Shobha Vasudevan, Wenjie (Joe) Jiang, David Bieber, Rishabh Singh, hamid shojaei, C. Richard Ho, Charles Sutton
NeurIPS 2021 | Conference PDF | Archive PDF | Plain Text | LLM Run Details
| Reproducibility Variable | Result | LLM Response |
|---|---|---|
| Research Type | Experimental | We evaluate Design2Vec on three real-world hardware designs, including the TPU, Google s industrial chip used in commercial data centers. Our results demonstrate that Design2Vec dramatically outperforms baseline approaches that do not incorporate the RTL semantics and scales to industrial designs. |
| Researcher Affiliation | Industry | Shobha Vasudevan Google Research, Brain Team shovasu@google.com Wenjie Jiang Google Research, Brain Team wenjiej@google.com David Bieber Google Research, Brain Team dbieber@google.com Rishabh Singh Google X rising@google.com Hamid Shojaei Google hamids@google.com Richard Ho Google riho@google.com Charles Sutton Google Research, Brain Team charlessutton@google.com |
| Pseudocode | Yes | Algorithm 1 Test Input Generation 1: Input: A set of uncovered points C = {C1, , Cm} 2: I = {} 3: while C = do 4: C = Pick Random Cover Point(C) 5: C = C \ C 6: for j = 1 . . . K do 7: {Optimize cover prob. wrt test parameters I} 8: I random() 9: while I has not converged do 10: I I + Iis_hit(C, I) 11: end while 12: I I.append(I) 13: end for 14: end while 15: return I |
| Open Source Code | No | Although the code is proprietary, we provide details about the model and architectures required to reproduce the main experimental results. |
| Open Datasets | Yes | We evaluate our methods on the three real-world designs from Table 6. For each design, we obtain training data by generating random tests and sampling each test parameter uniformly. ... (i) IBEX v1 [1], a RISC-V design (ii) IBEX v2, IBEX enhanced with security features, and (iii) Tensor Processing Unit (TPU) [23]... [1] IBEX RTL source. https://github.com/low RISC/ibex. |
| Dataset Splits | Yes | For this reason, we divide the data into training and test point by cover point, such that no cover point and no test occurs in both the training and validation set for the learned models. All results are the median over three random train-validation splits. |
| Hardware Specification | Yes | We train our models on a Cloud TPU v3-8 (8 cores). |
| Software Dependencies | No | The paper states models are implemented in Python using PyTorch, but does not specify version numbers for these or other software dependencies. |
| Experiment Setup | Yes | All models were trained for 100 epochs. We used Adam optimizer with a learning rate of 0.0001. Batch sizes of 64 for IBEX v1 and v2, and 128 for TPU were used. The hidden size for all GNNs and LSTMs was set to 64. For RTL IPA-GNN, we used 4 layers. For all GNNs, we used a token embedding of size 64. The input embedding size for MLP was set to 64. We used label smoothing with 𝜖 = 0.1 for the cross-entropy loss. |