Operator Mutexes and Symmetries for Simplifying Planning Tasks
Authors: Daniel Fišer, Álvaro Torralba, Alexander Shleyfman7586-7593
AAAI 2019 | Conference PDF | Archive PDF | Plain Text | LLM Run Details
| Reproducibility Variable | Result | LLM Response |
|---|---|---|
| Research Type | Experimental | We propose four different methods for inference of operator mutexes and experimentally verify that they can be found in a sizable number of planning tasks. Experimental Results The proposed methods were implemented in C and the source code is publicly available1. Table 1 summarizes the results on the number of inferred op-mutex pairs (in thousands). |
| Researcher Affiliation | Academia | Daniel Fiˇser Czech Technical University in Prague, Faculty of Electrical Engineering, Prague, Czech Republic, Alvaro Torralba Saarland University, Saarland Informatics Campus, Saarbr ucken, Germany, Alexander Shleyfman Technion Haifa, Israel |
| Pseudocode | Yes | Algorithm 1: Fixpoint computation of a redundant set. |
| Open Source Code | Yes | The proposed methods were implemented in C and the source code is publicly available1. 1https://gitlab.com/danfis/cplan.git, branch aaai19 |
| Open Datasets | Yes | We used all IPC benchmarks 2006 2018 from the optimal track. |
| Dataset Splits | No | The paper discusses 'train', 'validation', and 'test' as abstract components of a planning task (e.g., 'train' as a set of operators, 'validation' and 'test' as conceptual stages in a planning process like 'test set' for evaluation), but does not provide explicit details about data splits (e.g., percentages or counts) for experimental datasets. |
| Hardware Specification | Yes | The experiments were performed on a cluster with Intel E5-2670 2.6 GHz processor with 8 GB memory limit for each task. |
| Software Dependencies | No | The paper mentions implementation in C and using the BLISS library, but does not provide specific version numbers for these software components. |
| Experiment Setup | Yes | The experiments were performed on a cluster with Intel E5-2670 2.6 GHz processor with 8 GB memory limit for each task. We set the time limit to 30 minutes for the whole planning process. We used A* with the LM-Cut (lmc) heuristic, the merge-and-shrink (m&s) heuristic with SCCDFP merge strategy and non-greedy bisimulation shrink strategy, and the potential (pot) heuristic optimized for all syntactic states. |