Operator-Potential Heuristics for Symbolic Search
Authors: Daniel Fišer, Álvaro Torralba, Jörg Hoffmann9750-9757
AAAI 2022 | Conference PDF | Archive PDF | Plain Text | LLM Run Details
| Reproducibility Variable | Result | LLM Response |
|---|---|---|
| Research Type | Experimental | 8 Experimental Evaluation We implemented our search algorithm in C.3 Operators and facts are pruned with the h2 heuristic in forward and back-ward direction (Alc azar and Torralba 2015), and the translation from PDDL to FDR uses the inference of mutex groups proposed by Fiˇser (2020). We used all planning domains from the optimal track of International Planning Competitions (IPCs) from 1998 to 2018 excluding the ones containing conditional effects after translation. We merged, for each domain, all benchmark suites across different IPCs. This leaves 48 domains overall. We used a cluster of computing nodes with Intel Xeon Scalable Gold 6146 processors and CPLEX (I)LP solver v12.10. The time and memory limits were set to 30 minutes and 8 GB, respectively. |
| Researcher Affiliation | Academia | 1 Saarland University, Saarland Informatics Campus, Saarbr ucken, Germany 2 Czech Technical University in Prague, Faculty of Electrical Engineering, Czech Republic 3 Aalborg University, Denmark |
| Pseudocode | Yes | Algorithm 1: Symbolic forward A with a consistent operator-potential heuristic. |
| Open Source Code | Yes | 3https://gitlab.com/danfis/cpddl, branch aaai22-symba-op-pot |
| Open Datasets | Yes | We used all planning domains from the optimal track of International Planning Competitions (IPCs) from 1998 to 2018 excluding the ones containing conditional effects after translation. |
| Dataset Splits | No | The paper mentions using standard IPC domains but does not provide specific details on how these were split into training, validation, or test sets. |
| Hardware Specification | Yes | We used a cluster of computing nodes with Intel Xeon Scalable Gold 6146 processors and CPLEX (I)LP solver v12.10. |
| Software Dependencies | Yes | We used a cluster of computing nodes with Intel Xeon Scalable Gold 6146 processors and CPLEX (I)LP solver v12.10. |
| Experiment Setup | Yes | The time and memory limits were set to 30 minutes and 8 GB, respectively. We used a time limit of 30 seconds for applying mutexes on the goal BDD and 10 seconds for merging transition relation BDDs (Torralba et al. 2017). |