Notice: The reproducibility variables underlying each score are classified using an automated LLM-based pipeline, validated against a manually labeled dataset. LLM-based classification introduces uncertainty and potential bias; scores should be interpreted as estimates. Full accuracy metrics and methodology are described in [1].
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design
Authors: Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie
ICLR 2025 | Venue PDF | LLM Run Details
| Reproducibility Variable | Result | LLM Response |
|---|---|---|
| Research Type | Experimental | Evaluated on five different circuit design tasks, Circuit Fusion consistently outperforms the stateof-the-art supervised method specifically developed for every single task, demonstrating its generalizability and ability to learn circuits inherent properties1. 4 EXPERIMENTS Circuit dataset. We construct a dataset with 41 RTL designs collected from various representative open-source benchmarks (Corno et al., 2000; URL, b; Vex Riscv, 2022; Amid et al., 2020), with detailed statistics provided in Table 1. Table 2: Comparison between Circuit Fusion and baseline methods across all five design quality prediction tasks. Circuit Fusion consistently outperforms all baseline methods, including hardware solutions, general LLM-based text encoders, and software code encoders across all tasks. Figure 6: On the downstream task performance scaling with pre-trained Circuit Fusion model size and data size. |
| Researcher Affiliation | Academia | Wenji Fang Shang Liu Jing Wang Zhiyao Xie The Hong Kong University of Science and Technology EMAIL, EMAIL |
| Pseudocode | Yes | The detailed splitting algorithm is provided in Algorithm 1. Specifically, for each register, we apply a breadth-first search starting from that register, backtracing through all connected combinational logic until reaching the related input/output registers. Algorithm 1 Sub-circuit generation(s) 1: V {s} Set of visited nodes 2: Q {s} Queue with start node 3: R Set to store registers and inputs 4: while Q = do 5: u dequeue Q Current node 6: for all v u.outgoing do 7: if type(v) {reg, in} then 8: R R {v} Add register/input to set 9: continue Skip to next node 10: if v / V then 11: Q Q {v} Add unvisited node to queue 12: V V {v} Mark node as visited 13: v.set Parent(u) Set parent node 14: return R Return set of all registers and inputs |
| Open Source Code | Yes | Corresponding Author 1Circuit Fusion is available at: https://github.com/hkustzhiyao/CircuitFusion Open access to Circuit Fusion code: The source code for Circuit Fusion is publicly available at: https://github.com/hkust-zhiyao/CircuitFusion. The repository includes scripts with step-by-step instructions to replicate the primary results presented in this paper. |
| Open Datasets | Yes | We construct a dataset with 41 RTL designs collected from various representative open-source benchmarks (Corno et al., 2000; URL, b; Vex Riscv, 2022; Amid et al., 2020), with detailed statistics provided in Table 1. Dataset description: All datasets used in our experiments are from open-source benchmarks. A summary of these datasets is available in Appendix A, with a demonstration example shown in Appendix B.2. A.0.1 ITC 99 The ITC 99 benchmark suite (Corno et al., 2000) is a widely used collection of hardware circuit designs, primarily designed for logic synthesis and verification. A.0.2 OPENCORES The Open Cores repository (URL, b) offers open-source hardware designs, including a wide variety of digital systems, such as CPUs, memory controllers, communication protocols, etc. A.0.3 VEXRISCV Vex Riscv (Vex Riscv, 2022) is an open-source, RISC-V compliant CPU core designed using Spinal HDL. A.0.4 CHIPYARD Chipyard (Amid et al., 2020) is a comprehensive framework for building RISC-V-based system-onchip (SoC) designs. |
| Dataset Splits | Yes | We apply an 80/20 training/test split, ensuring the split is based on complete designs, with 33 designs used for training and 8 reserved for testing. |
| Hardware Specification | Yes | Experiments are conducted on a server equipped with a 2.9 GHz Intel Xeon(R) Platinum 8375C CPU and 512 GB RAM, with four NVIDIA A4000 GPUs for model pre-training. |
| Software Dependencies | No | Our Circuit Encoder is implemented in Python, utilizing Pytorch and DGL (Wang, 2019) for selfsupervised pre-training and model implementation. While Python, PyTorch, and DGL are mentioned, specific version numbers are not provided. |
| Experiment Setup | Yes | During the pre-training phase, the four self-supervised tasks are trained simultaneously for 50 epochs, with a total training time of approximately 20 hours. We use GELU as the activation function and set the batch size to 128. For optimization, we select Adam W, known for its ability to handle large-scale data effectively. The learning rate is warmed up to 1e-4 during the first 1000 iterations, after which it follows a cosine decay schedule, gradually reducing to 1e-5. For the contrastive learning tasks (i.e., Task #1, #2, and #4), we utilize the Info NCE loss function across all contrastive schemes. To balance the contributions of the different contrastive schemes, we assign an intra-modal weight of 1.0, while the cross-modal and implementation-aware weights are set to 0.2. All temperature parameters are set to 0.3. For masked graph modeling on both RTL and netlist sub-circuit graphs (used in Task #1 and netlist encoder), we adopt an approach inspired by Graph MAE (Hou et al., 2022). Specifically, 30% of the nodes in both the RTL and netlist graphs are randomly masked and reconstructed during each training epoch. A three-layer MLP with a hidden dimension of 256 is used to reconstruct the node types. |